DACs and analog-to-digital converters ("ADCs") have recently come into more widespread use with the development of suitable process technology and the increase in digital audio and video and other applications. One common type of DAC is the so-called "binary-weighted" DAC. Such DACs include a number of taps receiving different binary-weighted currents and a series of switches, connected to those taps, controlled by the input code. Binary-weighted DACs are described, for example, in Analog-Digital Conversion Handbook, Third Edition, by Analog Devices, Inc.
A simple binary-weighted DAC is shown in block diagram form in FIG. 1. As shown, the 3-bit DAC includes three current sources 12, 14 and 16 respectively producing four amps, two amps and one amp. Current source 12 is connected to line 18 and through switch S1 to output line 24. Current source 14 is connected to line 20 and through switch S2 to output line 24. Current source 16 is connected to line 22 and through switch S3 to output line 24. The digital input code is received on bus 26 and controls operation of the switches S1, S2 and S3.
During operation, the input code controls switches S1, S2 and S3 such that during closure of any one of the switches, the current from the corresponding current source will flow through the switch to the output line 24. The switches can be controlled such that they are closed and conduct current when they receive a logical 1. As will be appreciated by those skilled in the art, because of the binary-weighted nature of the current sources, the amount of total current received on output line 24 will be proportional to the input code received. An output buffer stage (not shown), possibly consisting of an operational amplifier, can be connected in series with output line 24 to convert the output current to a voltage and/or to provide amplification, and produce a low-impedance voltage output.
As a result of the operation of the switches, transient glitch energy may be produced causing inaccurate performance. For example, when the input code transitions from binary number 011 to binary number 100, all three switches, S1, S2 and S3 change state despite the fact that the input code has only incremented by binary 1. This action can cause transient glitch energy.
To avoid transient glitch energy problems associated with the switching in binary-weighted DACs, improved prior art DACs use what is referred to as "thermometer code" to control current source cells. An example of such a prior art DAC is shown in FIG. 2. FIG. 2 shows an 8-bit DAC 28 including two 4 to 15 converters 30 and 32. 4 to 15 converter 30 receives the four most significant bits ("MSBs") IN1, IN2, IN3 and IN4 of the digital input code and produces 15 outputs MOUT1-MOUT15. Similairly, 4 to 15 converter 32 receives the four least significant bits ("LSBs") IN5-IN8 of the digital input code and produces outputs LOUT1-LOUT15. The outputs MOUT1-MOUT15 and LOUT1-LOUT15 are referred to as "thermometer code" outputs. As will be appreciated by those skilled in the art, as the digital input code to the 4 to 15 converter is incremented by binary 1, only one of the outputs changes state.
The DAC 28 also includes 15 MSB current source cells MCELL1-MCELL15 and 15 LSB current source cells LCELL1-LCELL15. Each of the MSB current source cells MCELL1-MCELL15 is connected through one of the 15 switches MS1-MS15 to output summing node OUT. Similarly, each of the LSB current source cells LCELL1-LCELL15 is connected through one of the 15 switches LS1-LS15 to output summing node OUT. The outputs MOUT1-MOUT15 of 4 to 15 converter 30 control operation of the switches MS1-MS15. Similarly, the outputs LOUT1-LOUT15 of 4 to 15 converter 32 control operation of the switches LS1-LS15. The switches can be controlled such that they are closed and conduct current when they receive a logical 1.
During operation, 8-bit digital input code IN1-IN8 is received by the 4 to 15 converters. The 4 to 15 converters 30 and 32 convert the digital input code to outputs MOUT1-MOUT15 and LOUT1-LOUT15. Those outputs MOUT1-MOUT15 and LOUT1-LOUT15 control operation of the switches MS1-MS15 and LS1-LS15, respectively. The closed switches conduct currents from the MSB current source cells MCELL1-MCELL15 and the LSB current source cells LCELL1-LCELL15 and the currents are summed at node OUT. The output current (sum) can be provided to a buffer stage (not shown) for providing a low-impedance analog output and/or gain. As will be understood by those skilled in the art, because the thermometer code controls operation of the switches, when the input code increases or decreases by binary 1, only one of the switches MS1-MS15 and LS1-LS15 changes state, reducing the transient glitch error problem associated with binary-weighted DACS.
Each LSB current source cell LCELLn of the DAC can be implemented using CMOS technology. For example, the LSB cell can be realized with a PMOS transistor as shown in FIG. 3. As shown, the transistor has a gate, a source and a drain. The gate of the transistor is connected to node BIAS for receiving a bias voltage. The source is connected to node SUPPLY for receiving a supply voltage. When the bias voltage is large enough to turn on the transistor, the supply voltage produces a current which flows from the source to the drain. The transistor acts as a current source.
For simplicity and purposes of illustration, the CMOS current source cell will be shown, as illustrated in FIG. 4, as a block with a dot representing the drain of the transistor.
As will be understood by those skilled in the art, the MSB current source cells are typically larger (produce more current) than the LSB current source cells. For example, in the prior art DAC shown in FIG. 2, each of the MSB current source cells MCELL1-MCELL15 can be 16 times larger than each of the LSB current source cells, LCELL1-LCELL15. To implement each MSB current source cell, 16 LSB current source cells are added together. If each LSB current source cell includes one CMOS transistor, then each MSB current source cell includes 16 CMOS transistors (of the same value) connected in parallel (e.g., with the drains electrically tied together).
FIG. 5 schematically represents the electrical connections of the transistors and also is diagrammatic of the physical layout of the transistors. FIG. 5 shows a prior art layout for the transistors used to implement the MSB current source cells MCELL1-MCELL15 and the LSB current source cells LCELL1-LCELL15 of the DAC of FIG. 2. As shown, the layout includes an array of 240 transistors, desirably of equal value, each labeled T. The array includes 15 columns and 16 rows of transistors. Each transistor shown is labeled as T.sub.i,j where i and j represent the column and row, respectively, of the transistor. Only the transistors of columns 1, 2, 14 and 15 are shown for ease in illustration.
As shown, each LSB current source cell LCELL1-LCELL15 includes one transistor. In this prior art example, the current source cells LCELL1-LCELL15 include 15 of the 16 transistors T.sub.1,15 -T.sub.15,15 of column 15 of the array. A line drawn from the dot representing the drain of each transistor illustrates from where the current flows in each LSB cell.
Each MSB cell MCELL1-MCELL15 includes 16 transistors connected in parallel. Those connections are shown by a line connecting the dots representing the drains of the sixteen transistors. In this prior art example, MSB cell MCELL1 includes the parallel connection of the sixteen transistors T.sub.1,1 -T.sub.16,1 of column 1. Similarly, MSB cell MCELL2 includes the parallel connection of the sixteen transistors T.sub.1,2 -T.sub.16,2 of the transistors of column 2. Thus, as can be seen, each of the MSB cells MCELL1-MCELL15 includes the parallel connection of the sixteen transistors of the corresponding column of transistors in the array.
Ideally, the DAC should produce an analog output signal which linearly increases as the digital input code increases. However, as will be readily appreciated by those skilled in the art, the analog output signal of most DACs tends to be non-linear. DNL error is the deviation in the difference between two adjacent points in the transfer function (a graph of the analog output signal versus the digital input code) of the output voltage signal level from its ideal level. DNL errors in a DAC can effect the accuracy of the DAC and, if severe enough, can cause the DAC to be non-monotonic (one or more values of the analog output may actually be less than the values corresponding to smaller input codes).
DNL errors in such prior art DACs can be caused by gradients in the transistor values of the transistors within the array. The gradients are typically caused by process inaccuracies (i.e., fabrication inaccuracies such as faulty oxide irregularities, poor polysilicon etching or implant non-uniformities). Such process gradients can cause desirably identical transistors to pass different amounts of current. While current source DACs typically include a large number of transistors which ideally have the same value, (i.e., are of the same size and therefore pass the same amount of current), process gradients result in such transistors having different values. Although the adding of smaller current sources together (the MSB current sources include a number of LSB current sources added together) statistically increases the accuracy of the larger current sources, gradients across the array layout can cause DNL errors which negatively affect the accuracy and performance of the DAC. The gradients can be linear, non-linear or random.
In the prior art layout of FIG. 5, if a transistor process gradient (whether linear or non-linear) existed across the array from left to right, then the transistors of column 1 would have a very different value than the transistors of column 15. Therefore, MSB current source cell MCELL1 would generate a different amount of current than current source cell MCELL15. Additionally, MSB current source cell MCELL1 would not be equal to 16 times any of the LSB current source cells LCELL1-LCELL15 as desired. If the gradient is large enough, the resulting DNL error could cause inaccurate performance for the DAC.
Those skilled in the art will understand that a vertical gradient occurring across the array of the prior art layout of FIG. 5 would not cause DNL errors due to the arrangement. However, as will be appreciated by those skilled in the art, other prior art layouts (not shown) include the LSB current source cells arranged at any one of the top, bottom or either side of the array. Also, other prior art layouts include the MSB current source cells being alternatively added horizontally along the rows, instead of the columns as shown. In each of the prior art arrangements, a transistor gradient in one direction across the array could cause DNL errors.
Accordingly, a general object of the present invention is to provide a current source DAC having reduced DNL errors due to transistor process gradients.
Other objects and advantages will be apparent from the detailed description below.